About Digital Electronics

Following are some of the multiple choice questions on the Digital Electronics with answers that will help the students in developing their knowledge.

Digital Electronics MCQ

1. Convert the following decimal number to 8-bit binary.

  • 101110112
  • 110111012
  • 101111012
  • 101111002

2. In the boolean algebra, a variable has ________ different state(s)/value(s).

  • 3
  • 1
  • 2
  • 4

3. An AND gate will function as OR if

  • All the inputs to the gates are “1”
  • All the inputs are ‘0’
  • Either of the inputs is “1”
  • All the inputs and outputs are complemente'

4. Which of the following is Universal Gate?

  • OR gate
  • NAND gate
  • AND gate
  • NOR gate

5. The number of Boolean functions that can be generated by n variables is equal to

  • 2n
  • 22n
  • 2n-1
  • 2n

6. The inputs of a NAND gate are connected together. The resulting circuit is ___________.

  • OR gate
  • AND gate
  • NOT gate
  • None of the above

7. A 4-bit R/2R ladder digital-to-analog converter uses ________.

  • one resistor value
  • two resistor values
  • three resistor values
  • four resistor values

8. Among the logic families, the family which can be used at very high frequency greater than 100 MHz in a 4 bit synchronous counter is

  • TTLAS
  • CMOS
  • ECL
  • TTLLS

9. In Boolean algebra, the bar sign (-) indicates ___________.

  • OR operation
  • AND operation
  • NOT operation
  • None of the above

10. In which of the following base systems is 123 not a valid number?

  • Base 10
  • Base 16
  • Base 8
  • Base 3

11. The only function of NOT gate is to ___________.

  • Stop signal
  • Invert input signal
  • Act as a universal gate
  • None of the above

12. Which is a typical application of digital signal processing?

  • noise elimination
  • music signal processing
  • image processing
  • all of the above

13. A NAND gate is called a universal logic element because

  • It is used by everybody
  • Any logic function can be realized by NAND gates alone
  • All the minization techniques are applicable for optimum NAND gate realization
  • Many digital computers use NAND gates.

14. Most of the digital computers do not have floating point hardware because

  • Floating point hardware is costly
  • It is slower than software
  • It is not possible to perform floating point addition by hardware
  • Of no specific reason

15. Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins?

  • PLCC
  • QFP
  • PGA
  • BGA

16. Which is the example of digital device from the given option ?

  • Record players
  • Microprocessors
  • Sensors
  • Thermistors

17. How many 16K * 4 RAMs are required to achieve a memory with a capacity of 64K and a word length of 8 bits?

  • 2
  • 4
  • 6
  • 8

18. What must be done to interface TTL to CMOS?

  • a dropping resistor must be used on the cmos of 12 v supply to reduce it to 5 v for the ttl
  • as long as the cmos supply voltage is 5 v they can be interfaced (however, the fan- out of the ttl is limited to five cmos gates)
  • a 5 v zener diode must be placed across the inputs of the ttl gates in order to protect them from the higher output voltages of the cmos gates
  • a pull-up resistor must be used between the ttl output-cmos input node and vcc; the value of rp will depend on the number of cmos gates connected to the node

19. What causes low-power Schottky TTL to use less power than the 74XX series TTL?

  • the schottky-clamped transistor
  • a larger value resistor
  • the schottky-clamped mosfet
  • a small value resistor

20. What are the major differences between the 5400 and 7400 series of ICs?

  • the 5400 series are military grade and require tighter supply voltages and temperatures
  • the 5400 series are military grade and allow for a wider range of supply voltages and temperatures
  • the 7400 series are an improvement over the original 5400s
  • the 7400 series was originally developed by texas instruments and the 5400 series was brought out by national semiconductors after ti’s patents expired as a second supply source

21. What is ripple carry adder?

  • the carry output of the lower order stage is connected to the carry input of the next higher order stage
  • the carry input of the lower order stage is connected to the carry output of the next higher order stage
  • the carry output of the higher order stage is connected to the carry input of the next lower order stage
  • the carry input of the higher order stage is connected to the carry output of the lower order stage

22. How many select lines would be required for an 8-line-to-1-line multiplexer?

  • 2
  • 4
  • 8
  • 3

23. What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?

  • 0 to 2n
  • 0 to 2n + 1
  • 0 to 2n – 1 d) 0 to 2n+1/2
  • none of the above

24. What is the difference between a shift-right register and a shift-left register?

  • there is no difference
  • the direction of the shift
  • propagation delay
  • the clock input

25. What is the preset condition for a ring shift counter?

  • all ffs set to 1
  • all ffs cleared to 0
  • a single 0, the rest 1
  • a single 1, the rest 0

26. PAL refers to____________

  • programmable array loaded
  • programmable logic array
  • programmable array logic
  • programmable and logic

27. Dynamic RAM employs__________________

  • capacitor or mosfet
  • fet or jfet
  • capacitor or bjt
  • bjt or mos

28. Static RAM employs________________

  • bjt or mosfet
  • fet or jfet
  • capacitor or bjt
  • bjt or mos

29. The complex programmable logic device contains several PLD blocks and____________

  • a language compiler
  • and/or arrays
  • global interconnection matrix
  • field-programmable switches

30. The FPGA refers to_____________

  • first programmable gate array
  • field programmable gate array
  • first program gate array
  • field program gate array

31. The full form of VLSI is______________

  • very long single integration
  • very least scale integration
  • very large scale integration
  • very long scale integration

32. In FPGA, vertical and horizontal directions are separated by_______________

  • a line
  • a channel
  • a strobe
  • a flip-flop

33. Applications of PLAs are____________

  • registered pals
  • configurable pals
  • pal programming
  • all of the mentioned

34. CMOS refers to_______________

  • continuous metal oxide semiconductor
  • complementary metal oxide semiconductor
  • centred metal oxide semiconductor
  • concrete metal oxide semiconductor

35. Fan-in is defined as______________

  • the number of outputs connected to gate without any degradation in the voltage levels
  • the number of inputs connected to gate without any degradation in the voltage levels
  • the number of outputs connected to gate with degradation in the voltage levels
  • the number of inputs connected to gate with degradation in the voltage levels

36. The maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its output is termed as_____________

  • noise margin
  • noise immunity
  • white noise
  • signal to noise ratio

37. The full form of CML is____________

  • complementary mode logic
  • current mode logic
  • collector mode logic
  • collector mixed logic

38. Propagation delay is defined as

  • the time taken for the output of a gate to change after the inputs have changed
  • the time taken for the input of a gate to change after the outputs have changed
  • the time taken for the input of a gate to change after the intermediates have changed
  • the time taken for the output of a gate to change after the intermediates have changed

39. Propagation delay times can be divided as

  • t(plh) and t(lph)
  • t(lph) and t(phl)
  • t(plh) and t(phl)
  • t(hpl) and t(lph)

40. Power Dissipation in DIC is expressed in

  • watts or kilowatts
  • milliwatts or nanowatts
  • db
  • mdb

41. If a PAL has been programmed once

  • its logic capacity is lost
  • its outputs are only active high
  • its outputs are only active low
  • it cannot be reprogrammed

42. The difference between a PAL & a PLA is

  • pals and plas are the same thing
  • the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane
  • the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane
  • the pal has more possible product terms than the pla

43. Which type of device FPGA are?

  • sld
  • srom
  • eprom
  • pld

44. For programmable logic functions, which type of PLD should be used?

  • pla
  • pal
  • cpld
  • sld

45. Outputs of the AND gate in PLD is known as                          

  • input lines
  • output lines
  • strobe lines
  • control lines

46. How many address bits are required to select memory location in Memory decoder?

  • 4 kb
  • 8 kb
  • 12 kb
  • 16 kb

47. How many types of PLD is?

  • 2
  • 3
  • 4
  • 5

48. PLA contains                          

  • and and or arrays
  • nand and or arrays
  • not and and arrays
  • nor and or arrays

49. PLA is used to implement                          

  • a complex sequential circuit
  • a simple sequential circuit
  • a complex combinational circuit
  • a simple combinational circuit

50. A PLA is similar to a ROM in concept except that                          

  • it hasn’t capability to read only
  • it hasn’t capability to read or write operation
  • it doesn’t provide full decoding to the variables
  • it hasn’t capability to write only

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